DocumentCode
1869940
Title
3-Transistor antifuse OTP ROM array using standard CMOS process
Author
Jinbong Kim ; Kwyro Lee
Author_Institution
Dept. of EECS, KAIST, Taejon, South Korea
fYear
2003
fDate
12-14 June 2003
Firstpage
239
Lastpage
242
Abstract
A 3-transistor cell CMOS OTP ROM array using CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high voltage (HV) blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed structure can be a viable technology option as a high density OTP ROM array for modern digital as well as analog circuits.
Keywords
CMOS memory circuits; MOSFET; PROM; semiconductor device breakdown; MOSFET gate oxide breakdown; analog circuits; cell access transistor; digital circuits; nMOS antifuse; three transistor antifuse CMOS one-time programmable ROM array; Analog circuits; CMOS analog integrated circuits; CMOS process; CMOS technology; Electric breakdown; MOS devices; Power supplies; Random access memory; Read only memory; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-89114-034-8
Type
conf
DOI
10.1109/VLSIC.2003.1221214
Filename
1221214
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