Title :
A 90 nm low power 32 K-byte embedded SRAM with gate leakage suppression circuit for mobile applications
Author :
Nii, K. ; Tenoh, Y. ; Yoshizawa, T. ; Imaoka, S. ; Tsukamoto, Y. ; Yamagami, Y. ; Suzuki, T. ; Shibayama, A. ; Makino, H. ; Iwade, S.
Author_Institution :
Syst. LSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
In sub 100 nm generation, gate tunneling leak current increases and dominates total standby leak current of LSI based on decreasing gate oxide thickness. We propose reducing gate leak current in SRAM using Local DC Level Control (LDLC) and an Automatic Gate Leakage Suppression Driver to reduce gate leak current in the peripheral circuit. We designed and fabricated a 32 KB 1-port SRAM using 90 nm CMOS technology. The 6T-SRAM-cell size is 1.25 /spl mu/m/sup 2/. Evaluation showed that the standby current of 32 KB SRAM is 1.2 /spl mu/A at 1.2 V and room temperature. It is reduced to 7.5% of conventional SRAM.
Keywords :
CMOS integrated circuits; SRAM chips; leakage currents; level control; tunnelling; 1.2 V; 1.2 muA; 100 nm; 293 to 298 K; 90 nm; CMOS technology; SRAM; automatic gate leakage suppression driver; cell size; gate leakage suppression circuit; gate oxide; gate tunneling leak current; mobile applications; peripheral circuit; room temperature; CMOS technology; Driver circuits; Gate leakage; Large scale integration; Leakage current; Level control; Random access memory; Standby generators; Temperature; Tunneling;
Conference_Titel :
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-034-8
DOI :
10.1109/VLSIC.2003.1221217
