A novel fractional-N PLL architecture with hybrid of DCO and VCO

Author

Chao He ; Kwasniewski, T.

Author_Institution

DOE, Carleton Univ., Ottawa, ON, Canada

fYear

2012

fDate

April 29 2012-May 2 2012

Firstpage

1

Lastpage

4

Abstract

A novel fractional-N Phase-Lock Loop (PLL) architecture is proposed in this paper. The architecture features a hybrid of DCO and VCO, which is controlled by a mixed-mode loop filter. The analog part of the filter works as the proportional path of the loop and the digital part as the integral path. The proposed architecture takes advantages of both analog PLL and All Digital PLL (ADPLL) and overcomes some problems encountered with each technique. The proposed solution has been verified in the behavioral level and a chip is under development.

Keywords

filters; phase locked loops; voltage-controlled oscillators; ADPLL; DCO; VCO; all digital PLL; analog PLL; digital controlled oscillator; fractional-N PLL architecture; fractional-N phase-lock loop; mixed-mode loop filter; voltage controlled oscillator; Arrays; Digital filters; Phase frequency detector; Phase locked loops; Tuning; Varactors; Voltage-controlled oscillators; DVCO; PLL; fractional-N; integral path; proportional path;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical & Computer Engineering (CCECE), 2012 25th IEEE Canadian Conference on

Conference_Location

Montreal, QC

ISSN

0840-7789

Print_ISBN

978-1-4673-1431-2

Electronic_ISBN

0840-7789

Type

conf

DOI

10.1109/CCECE.2012.6334992

Filename

6334992