Title :
A floating-gate-MOS-based low-power CDMA matched filter employing capacitance disconnection technique
Author :
Yamasaki, T. ; Fukuda, T. ; Shibata, T.
Author_Institution :
Dept. of Electron. Eng., Tokyo Univ., Japan
Abstract :
Low-power and compact CDMA matched filters have been developed based on the floating-gate MOS technology. The low-power operation has been achieved by employing the single-step matching scheme and disconnecting the coupling-capacitors unnecessary for the matching operation. The 255-chip matched filter fabricated in a 0.35-/spl mu/m technology demonstrated 6 mW operation at 3 V power supply and the chip rate of 5 MS/S, while occupying the chip area of 1.0 mm/sup 2/.
Keywords :
code division multiple access; digital filters; digital signal processing chips; matched filters; 0.35 micron; 3 V; 6 mW; capacitance disconnection; coupling-capacitors; floating gate MOS based low power CDMA matched filter; low power operation; Capacitance; Charge coupled devices; Circuits; Clocks; Energy consumption; Informatics; Matched filters; Multiaccess communication; Power dissipation; Power supplies;
Conference_Titel :
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-034-8
DOI :
10.1109/VLSIC.2003.1221223
