An Adder Based Hardware Architecture for the MPEG-4 Shape Adaptive IDCT

The recent trend of multimedia application convergence on mobile devices is challenged by the limited battery life of such devices. One such feature is MPEG-4 object-based video decoding, built upon algorithms like the shape adaptive inverse discrete cosine transform (SA-IDCT), which allows content-based interactivity. The dynamic nature of the SA-IDCT processing steps poses significant VLSI implementation challenges and many of the previously proposed approaches use area and power consumptive multipliers. We propose a new multiplier-less serial datapath based solely on adders and multiplexers to improve area and power enhanced by local clock gating. Our design implements the SA-IDCT realignment steps with efficient addressing logic and a transpose memory RAM. The entire design has been synthesized using the TSMC 0.09 mum TCBN90LP library, and performs well in benchmarking against prior art