Input pattern classification for transistor level testing of BiCMOS circuits

Author

Menon, Sankaran M. ; Jayasumana, Anura P. ; Malaiya, Yashwant K.

Author_Institution

Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA

fYear

1994

fDate

25-28 Apr 1994

Firstpage

457

Lastpage

462

Abstract

In BiCMOS, transistor stuck-OPEN faults exhibit delay faults in addition to sequential behavior. Stuck-ON faults cause enhanced I_DDQ. The faulty behavior of Bipolar (TTL) and CMOS logic families is compared with BiCMOS. The faults in BiCMOS devices cause one or more parts (p-part or n-parts) of the circuit to exhibit a different state (conducting or nonconducting) from the fault-free circuit. An input pattern classification scheme is presented for different faults. These classes of patterns are then used to obtain test sets

Keywords

BiCMOS integrated circuits; automatic testing; fault location; integrated circuit testing; logic testing; BiCMOS circuits; IC defects; conducting state; fault-free circuit; input pattern classification; nonconducting state; pattern classes; stuck-ON faults; stuck-OPEN faults; test sets; transistor level testing; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Circuit faults; Circuit testing; Delay; Logic devices; Logic functions; Pattern classification; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1994. Proceedings., 12th IEEE

Conference_Location

Cherry Hill, NJ

Print_ISBN

0-8186-5440-6

Type

conf

DOI

10.1109/VTEST.1994.292273

Filename

292273