Impact of behavioral modifications for testability

Author

Thomas, Thomas ; Vishakantantaiah, P. ; Abraham, Jacob A.

Author_Institution

Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA

fYear

1994

fDate

25-28 Apr 1994

Firstpage

427

Lastpage

432

Abstract

Behavioral specification of a VLSI design can be used to suggest behavioral modifications that improve testability of the design. Past work has been targeted at identifying the techniques that will enable such modifications. However, the impact of such behavioral modifications on the testability of a design has not been analyzed with regards to fault coverage and area overhead which is the focus of this paper. Results obtained show that the area overhead is low and the fault coverage is higher when the behavior is modified for testability. These results are compared with the results obtained when partial scan is used to improve the testability of a design

Keywords

VLSI; circuit CAD; design for testability; digital integrated circuits; integrated circuit testing; DFT; VLSI design; area overhead; behavioral modifications; behavioral specification; fault coverage; testability; Circuit faults; Circuit synthesis; Circuit testing; Design automation; Design for testability; Hardware design languages; Jacobian matrices; Process design; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1994. Proceedings., 12th IEEE

Conference_Location

Cherry Hill, NJ

Print_ISBN

0-8186-5440-6

Type

conf

DOI

10.1109/VTEST.1994.292278

Filename

292278