CMOS bridging fault modeling

Author

Renovell, M. ; Huc, P. ; Bertrand, Y.

Author_Institution

Lab. d´´Inf., Univ. des Sci. et Tech. du Languedoc, Montpellier, France

fYear

1994

fDate

25-28 Apr 1994

Firstpage

392

Lastpage

397

Abstract

This paper analyses the general problem of the determination of the intermediate potentials created by a bridging fault. The analyses is made taking into account the bridge resistance value. It is shown that the fault is detectable as a logic error for a given range of bridge resistance values. But, in this range, the logic faulty value is independent of the bridge resistance value. A general electrical model which can be used to determine if a particular structure of transistors gives an intermediate voltage which is higher or lower than a given threshold voltage is proposed. A global procedure to simulate bridging fault is given. By using the proposed equations and model no SPICE simulation is required

Keywords

CMOS integrated circuits; VLSI; combinatorial circuits; integrated logic circuits; logic gates; logic testing; CMOS bridging fault; VLSI; bridge resistance value; electrical model; fault modeling; global procedure; intermediate potentials; logic error; logic faulty value; logic nodes; threshold voltage; Bridge circuits; CMOS technology; Circuit faults; Circuit simulation; Electric resistance; Electrical fault detection; Logic gates; Semiconductor device modeling; Testing; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1994. Proceedings., 12th IEEE

Conference_Location

Cherry Hill, NJ

Print_ISBN

0-8186-5440-6

Type

conf

DOI

10.1109/VTEST.1994.292283

Filename

292283