CMOS bridging fault modeling

This paper analyses the general problem of the determination of the intermediate potentials created by a bridging fault. The analyses is made taking into account the bridge resistance value. It is shown that the fault is detectable as a logic error for a given range of bridge resistance values. But, in this range, the logic faulty value is independent of the bridge resistance value. A general electrical model which can be used to determine if a particular structure of transistors gives an intermediate voltage which is higher or lower than a given threshold voltage is proposed. A global procedure to simulate bridging fault is given. By using the proposed equations and model no SPICE simulation is required