Fault detection and fault localization using IDDQ-testing in parallel testable FAST-SRAMs

This paper contributes to the area of I_DDQ-testing of SRAMs by extending fault detection to transition coupling and neighborhood pattern sensitive faults. Furthermore I_DDQ-testing is expanded to fault localization. To accelerate existing test procedures of RAMs, associative search based test algorithms are modified with I_DDQ-testability for use in so called FAST-RAMs, which are designed to be tested in parallel. This method reduces the complexity of existing test algorithms by one or two orders. The chip area to implement FAST-testability runs up to a few per cent or per mille depending on the RAM architecture. Circuit details are discussed and compared with existing SRAM testing