DocumentCode
1871185
Title
On robustness of required random test length with regard to fault occurrence hypotheses
Author
Crépaux, S. ; Jacomino, M. ; David, R.
Author_Institution
CNRS, Grenoble, France
fYear
1994
fDate
25-28 Apr 1994
Firstpage
348
Lastpage
355
Abstract
For random test length evaluation, the usual approach considers only the fault that is most difficult to detect; this is pessimistic. The fault distribution in the batch of tested circuits should be taken into account. Since this information is not known before the test experiment, hypotheses on fault occurrence probabilities have to be made. This paper shows, through several simulations, that the test length does not depend very much on the fault occurrence hypotheses
Keywords
combinatorial circuits; fault location; logic testing; probability; combinational circuits; fault distribution; fault occurrence; fault occurrence probabilities; random test length evaluation; tested circuit batch; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Computer aided manufacturing; Digital circuits; Electrical fault detection; Fault detection; Probability; Robustness;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location
Cherry Hill, NJ
Print_ISBN
0-8186-5440-6
Type
conf
DOI
10.1109/VTEST.1994.292290
Filename
292290
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