DocumentCode
1871214
Title
Fault probabilities in routing channels of VLSI standard cell designs
Author
Spiegel, Gerald
Author_Institution
Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
fYear
1994
fDate
25-28 Apr 1994
Firstpage
340
Lastpage
347
Abstract
Two algorithms for the extraction of bridging and break faults from routing channels of VLSI standard cell designs are presented. Using an improved method for critical area calculation the probability of occurrence is determined for each fault. An experimental analysis of actual layouts shows the feasibility of the approach
Keywords
VLSI; application specific integrated circuits; cellular arrays; circuit analysis computing; circuit layout CAD; fault location; network routing; probability; VLSI standard cell designs; break faults; bridging faults; channel; critical area calculation; fault extraction; fault probabilities; layouts; Algorithm design and analysis; Circuit faults; Circuit testing; Costs; Fault tolerance; Integrated circuit layout; Integrated circuit manufacture; Probability; Routing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location
Cherry Hill, NJ
Print_ISBN
0-8186-5440-6
Type
conf
DOI
10.1109/VTEST.1994.292291
Filename
292291
Link To Document