Title :
Automating the verification of memory tests
Author :
van de Goor, A.J. ; Smit, B.
Author_Institution :
Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
Abstract :
Verification, consisting of completeness and irredundancy proofs for memory tests, can be quite complicated. This paper presents a method to automatically verify march tests for any type of fault. This method can be adapted for any other (non march) memory test. It presents a way of, mathematically, modeling faults and describes how the verification process has been automated
Keywords :
SRAM chips; fault location; finite state machines; integrated circuit testing; SRAM tests; completeness proofs; fault modelling; irredundancy proofs; march tests; memory tests; verification process automation; Automata; Automatic testing; Decoding; Fault detection; Fault diagnosis; Mathematical model; Random access memory; Writing;
Conference_Titel :
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location :
Cherry Hill, NJ
Print_ISBN :
0-8186-5440-6
DOI :
10.1109/VTEST.1994.292295
