Title :
A low power D3L 16-bit radix- 4 pipelined SRT divider
Author :
Pourashraf, S. ; Sayedi, Sayed Masoud
Author_Institution :
ECE Dept., Isfahan Univ. of Technol., Isfahan, Iran
fDate :
April 29 2012-May 2 2012
Abstract :
In this paper a 16-bit radix-4 pipelined divider implemented in a modified version of D3L family structure is presented. Performance of the circuit is evaluated and presented at different simulation corners. The results show that, compared with its dynamic version, the proposed circuit has lower power consumption and higher speed. Latency of the divider is equal to 10 half clock cycles. The circuit is designed in TSMC_180 nm CMOS process.
Keywords :
CMOS integrated circuits; circuit simulation; clocks; frequency dividers; logic circuits; D3L family structure; TSMC 180 nm CMOS process; circuit simulation; data driven dynamic logic; low power D<;sup>;3<;/sup>;L 16-bit radix- 4 pipelined SRT divider; power consumption; size 180 nm; Adders; Clocks; Delay; MOSFETs; Power demand; Topology; Data Driven Dynamic Logic; Energy reduction; Latency; SRT divider; Speed;
Conference_Titel :
Electrical & Computer Engineering (CCECE), 2012 25th IEEE Canadian Conference on
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4673-1431-2
Electronic_ISBN :
0840-7789
DOI :
10.1109/CCECE.2012.6335043
