DocumentCode :
1871385
Title :
Weighted random robust path delay testing of synthesized multilevel circuits
Author :
Wang, Weili ; Gupta, Sandeep K.
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
fYear :
1994
fDate :
25-28 Apr 1994
Firstpage :
291
Lastpage :
297
Abstract :
Importance of delay testing is growing especially for high speed circuits. Delay testing using automatic test equipment is expensive. Built-in self-test can significantly reduce the cost of comprehensive delay testing by replacing the test equipment. It was found that several multilevel, synthesized, robust path delay testable circuits require impractically long pseudo-random test sequences. Weighted random testing techniques have been developed for robust path delay testing. The proposed technique is successfully applied to these circuits and 100% robust path delay fault coverage obtained using only 1-2 sets of weights
Keywords :
built-in self test; integrated circuit testing; logic testing; many-valued logics; built-in self-test; high speed circuits; propagation delay; robust path delay fault coverage; synthesized multilevel circuits; test pattern generators; weighted random robust path delay testing; Automatic test equipment; Automatic testing; Built-in self-test; Circuit faults; Circuit synthesis; Circuit testing; Costs; Delay; Robustness; Test equipment;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location :
Cherry Hill, NJ
Print_ISBN :
0-8186-5440-6
Type :
conf
DOI :
10.1109/VTEST.1994.292298
Filename :
292298
Link To Document :
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