On broad-side delay test

A broad-side delay test is a form of a scan-based delay test, where the first vector of the pair is scanned into the chain, and the second vector of the pair is the combinational circuit´s response to this first vector. This delay test form is called “broad-side” since the second vector of the delay test pair is provided in a broad-side fashion, namely through the logic. This paper concentrates on generation of broad-side delay test vectors; shows the results of experiments conducted on the ISCAS sequential benchmarks, and discusses some concerns of the broad-side delay test strategy