Title :
Realization of fully path-delay-fault testable non-scan sequential circuits
Author :
Ke, Wuudiann ; Menon, P.R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
We present a new approach to synthesizing fully path-delay-fault testable non-scan sequential circuits. Two methods are proposed. Given the state transition graph of a finite state machine, one of our methods generates a fully robustly testable circuit while the other method, which may lead to more area-efficient circuits, guarantees robust or validatable non-robust tests for all paths
Keywords :
delays; design for testability; finite state machines; graph theory; logic design; logic testing; sequential circuits; FSM; finite state machine; fully path-delay-fault testable circuits; logic circuits; nonscan sequential circuits; state transition graph; Automata; Circuit faults; Circuit synthesis; Circuit testing; Delay; Input variables; Robustness; Sequential analysis; Sequential circuits; Signal synthesis;
Conference_Titel :
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location :
Cherry Hill, NJ
Print_ISBN :
0-8186-5440-6
DOI :
10.1109/VTEST.1994.292300
