DocumentCode
1871418
Title
Realization of fully path-delay-fault testable non-scan sequential circuits
Author
Ke, Wuudiann ; Menon, P.R.
Author_Institution
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
fYear
1994
fDate
25-28 Apr 1994
Firstpage
278
Lastpage
283
Abstract
We present a new approach to synthesizing fully path-delay-fault testable non-scan sequential circuits. Two methods are proposed. Given the state transition graph of a finite state machine, one of our methods generates a fully robustly testable circuit while the other method, which may lead to more area-efficient circuits, guarantees robust or validatable non-robust tests for all paths
Keywords
delays; design for testability; finite state machines; graph theory; logic design; logic testing; sequential circuits; FSM; finite state machine; fully path-delay-fault testable circuits; logic circuits; nonscan sequential circuits; state transition graph; Automata; Circuit faults; Circuit synthesis; Circuit testing; Delay; Input variables; Robustness; Sequential analysis; Sequential circuits; Signal synthesis;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location
Cherry Hill, NJ
Print_ISBN
0-8186-5440-6
Type
conf
DOI
10.1109/VTEST.1994.292300
Filename
292300
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