Clock tree structure with reduced wire length using the matched-delay skew compensation technique

In this paper we propose a new approach to balance skew in the clock network by manipulating the operating speed of the flip-flop. Six versions of the master-slave flip-flop with different data to output (T_DQ) delays are used in a matched-delay skew compensation technique. The T_DQ delay in each version of the flip-flop was increased by increasing the channel length of transistors in intermediate stages of the flip-flop. Distributing flip-flops according to their delay requirements reduces the effect of clock skew on the outputs of sequentially adjacent flip-flops. Furthermore, it increases skew bounds required by algorithms to balance the skew in the clock distribution network leading to reduced design complexity. Constructing five benchmark clock trees with a Modified Deferred Merge Embedding (MDME) algorithm with four, five, and six versions of the flip-flop shows that the matched-delay skew compensation technique can compensate for a skew up to 15% of the clock period. In addition, matched-delay skew compensation achieves a reduction in total wire length and wire elongation up to 16.6% and 56.8%, respectively, as compared to the traditional DME algorithm with only one flip-flop.