A new functional fault model for system-level descriptions

Author

Camurati, P. ; Corno, F. ; Meo, M. ; Prinetto, P.

Author_Institution

Dipartimento di Autom. e Inf., Politecnico di Torino, Italy

fYear

1994

fDate

25-28 Apr 1994

Firstpage

214

Lastpage

219

Abstract

Process algebras are a suitable formalism both for system-level description and for ATPG with formal verification techniques. A functional fault model for system-level descriptions is presented and experimental data are reported. The contributions of this paper are the definition of a general-purpose fault model for concurrently evolving processes and the implementation of a test pattern generation procedure, as a variant of the testing equivalence proof. A complete test system is implemented, allowing one to describe systems, describe faults and generate test patterns within the same environment

Keywords

automatic testing; digital integrated circuits; fault location; integrated circuit testing; integrated logic circuits; logic testing; ATPG; functional fault model; general-purpose fault model; system-level descriptions; test pattern generation procedure; Algebra; Automatic test pattern generation; Carbon capture and storage; Councils; Formal verification; Hardware; Mathematical model; Software testing; System testing; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1994. Proceedings., 12th IEEE

Conference_Location

Cherry Hill, NJ

Print_ISBN

0-8186-5440-6

Type

conf

DOI

10.1109/VTEST.1994.292310

Filename

292310