Neural models for transistor and mixed-level test generation

Author

Cooper, Carolina L C ; Bushnell, Michael L.

Author_Institution

Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA

fYear

1994

fDate

25-28 Apr 1994

Firstpage

208

Lastpage

213

Abstract

We derive new neural network models for n and pFET transistors for use in switch-level test generation. Special characteristics included in the model are bidirectionality and an explicit representation of the substrate. We prove the optimality of these models. The results for an example CMOS circuit indicate that modeling circuit portions at the switch-level allows more accurate tests for transistor stuck-open faults without giving up the speed of gate-level ATPG

Keywords

CMOS integrated circuits; Hopfield neural nets; automatic testing; insulated gate field effect transistors; integrated circuit testing; integrated logic circuits; logic testing; semiconductor device models; CMOS circuit; mixed-level test generation; nMOSFET; neural network models; pMOSFET; substrate representation; switch-level test generation; transistor stuck-open faults; Automatic test pattern generation; CMOS logic circuits; Circuit faults; Circuit testing; Logic circuits; Logic devices; Neural networks; Neurons; Semiconductor device modeling; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1994. Proceedings., 12th IEEE

Conference_Location

Cherry Hill, NJ

Print_ISBN

0-8186-5440-6

Type

conf

DOI

10.1109/VTEST.1994.292311

Filename

292311