DocumentCode
1871741
Title
A performance prediction model for the CUDA GPGPU platform
Author
Kothapalli, Kishore ; Mukherjee, Rishabh ; Rehman, M. Suhail ; Patidar, Suryakant ; Narayanan, P.J. ; Srinathan, Kannan
Author_Institution
Int. Inst. of Inf. Technol., Hyderabad, India
fYear
2009
fDate
16-19 Dec. 2009
Firstpage
463
Lastpage
472
Abstract
The significant growth in computational power of modern Graphics Processing Units (GPUs) coupled with the advent of general purpose programming environments like NVIDIA´s CUDA, has seen GPUs emerging as a very popular parallel computing platform. Till recently, there has not been a performance model for GPGPUs. The absence of such a model makes it difficult to definitively assess the suitability of the GPU for solving a particular problem and is a significant impediment to the mainstream adoption of GPUs as a massively parallel (super)computing platform. In this paper we present a performance prediction model for the CUDA GPGPU platform. This model encompasses the various facets of the GPU architecture like scheduling, memory hierarchy, and pipelining among others. We also perform experiments that demonstrate the effects of various memory access strategies. The proposed model can be used to analyze pseudo code for a CUDA kernel to obtain a performance estimate, in a way that is similar to performing asymptotic analysis. We illustrate the usage of our model and its accuracy with three case studies: matrix multiplication, list ranking, and histogram generation.
Keywords
coprocessors; matrix multiplication; memory architecture; parallel architectures; pipeline processing; processor scheduling; programming environments; CUDA GPGPU platform; CUDA kernel; GPU architecture; NVIDIA; asymptotic analysis; computational power; general purpose programming environments; graphics processing units; histogram generation; list ranking; matrix multiplication; memory access strategy; memory hierarchy; parallel computing platform; parallel supercomputing platform; performance prediction model; pipelining; scheduling; Concurrent computing; Graphics; Impedance; Kernel; Memory architecture; Parallel processing; Performance analysis; Pipeline processing; Predictive models; Programming environments;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Computing (HiPC), 2009 International Conference on
Conference_Location
Kochi
Print_ISBN
978-1-4244-4922-4
Electronic_ISBN
978-1-4244-4921-7
Type
conf
DOI
10.1109/HIPC.2009.5433179
Filename
5433179
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