• DocumentCode
    1871776
  • Title

    Correlating defect level to final test fault coverage for modular structured designs [microcontroller family]

  • Author

    Powell, Theo J. ; Butler, Kenneth M. ; Ales, Mike ; Haley, Roy ; Perry, Mark

  • Author_Institution
    Texas Instrum. Inc., Dallas, TX, USA
  • fYear
    1994
  • fDate
    25-28 Apr 1994
  • Firstpage
    192
  • Lastpage
    196
  • Abstract
    The Texas Instruments TMS370 is in volume production. Sample manufacturing data has been collected to correlate stuck fault grades to the defect levels that would have been realized at those grades, at both the module and chip levels. Since the chip is composed of test isolatable modules, the data collected provide insights into the randomness of the distribution of failures among the modules. Further analysis shows good agreement between actual data and theoretical defect level model predictions. The data emphasize the need for hash fault coverages and correspondingly required DFT practices in today´s era of “Six Sigma” quality targets
  • Keywords
    CMOS integrated circuits; computer testing; design for testability; failure analysis; fault location; integrated circuit testing; microcontrollers; quality control; TMS370; Texas Instruments; defect level model predictions; defect levels; final test fault coverage; modular structured designs; sample manufacturing data; scan DFT; scan design; six sigma quality targets; stuck fault grades; test isolatable modules; Circuit faults; Electrostatic discharge; Instruments; Integrated circuit manufacture; Mathematical model; Predictive models; Pulp manufacturing; Semiconductor device modeling; Testing; Virtual manufacturing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 1994. Proceedings., 12th IEEE
  • Conference_Location
    Cherry Hill, NJ
  • Print_ISBN
    0-8186-5440-6
  • Type

    conf

  • DOI
    10.1109/VTEST.1994.292314
  • Filename
    292314