• DocumentCode
    1871793
  • Title

    Analysis of the FinFET parasitics for improved RF performances

  • Author

    Parvais, B. ; Dehan, M. ; Subramanian, V. ; Mercha, A. ; San, K. Tamer ; Jurczak, M. ; Groeseneken, G. ; Sansen, W. ; Decoutere, S.

  • Author_Institution
    IMEC, Leuven
  • fYear
    2007
  • fDate
    1-4 Oct. 2007
  • Firstpage
    37
  • Lastpage
    38
  • Abstract
    FinFET architecture results in high level of parasitics that offset the performance gain that can be achieved through gate length scaling. In this work, we investigate technological solutions both at the process integration and layout levels to alleviate these limitations. Layout guidelines are derived to improve the RF performance. For an optimized layout folding, experiments indicate 15% gain in fT.
  • Keywords
    insulated gate field effect transistors; integrated circuit layout; radiofrequency integrated circuits; FinFET architecture; RF performance; gate length scaling; optimized layout folding; parasitic capacitance; Conference proceedings; FinFETs; Guidelines; Instruments; Integrated circuit interconnections; MOSFETs; Parasitic capacitance; Performance analysis; Radio frequency; Roentgenium;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, 2007 IEEE International
  • Conference_Location
    Indian Wells, CA
  • ISSN
    1078-621X
  • Print_ISBN
    978-1-4244-0879-5
  • Electronic_ISBN
    1078-621X
  • Type

    conf

  • DOI
    10.1109/SOI.2007.4357841
  • Filename
    4357841
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1871793