Title :
Determination of steady state voltage stability limit of a power system in the presence of SVC
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore
Abstract :
This paper proposes a simple and direct method of determining the steady state voltage stability limit of a power system when equipped with a static VAr compensator (SVC). The maximum permissible loading of a particular bus in a power system is determined through a simplified equivalent model of the original system. The method is very efficient and does not require repetitive load flow simulations to generate the system P-V or Q-V curve. The effectiveness of the proposed method is then tested on a simple 2-bus system and the IEEE 14-bus system. The effects of load power factor and SVC rating on voltage stability limit are also studied. The maximum permissible bus loading obtained by the proposed method in the IEEE system are also verified through repetitive load flow simulations and are found to be in excellent agreement
Keywords :
load flow; power factor; power system dynamic stability; static VAr compensators; 2-bus system; FACTS; IEEE 14-bus system; IEEE system; SVC rating; load power factor; maximum permissible bus loading; maximum permissible loading; power system; repetitive load flow simulations; simplified equivalent model; static VAr compensator; steady state voltage stability; system P-V curve; system Q-V curve; voltage stability limit; Capacitors; Load flow; Load flow analysis; Power system modeling; Power system simulation; Power system stability; Reactive power; Static VAr compensators; Steady-state; Voltage;
Conference_Titel :
Power Tech Proceedings, 2001 IEEE Porto
Conference_Location :
Porto
Print_ISBN :
0-7803-7139-9
DOI :
10.1109/PTC.2001.964748