Interleaving optimization in synchronous rectified DC/DC converters

Interleaving in synchronous rectifiers can lead to reduced losses in both the active and passive components. However, this depends on selecting the correct number of phases and the correct phase inductance for a particular application and requirements. In this paper optimizing the number of phases and the phase inductance is considered to maximize the interleaved synchronous rectifiers efficiency over the desired operating range. To do this, the RMS currents and losses in the bus capacitors, the phase inductances and the switching devices as a function of the number of phases and duty cycle are considered. Generic equations are presented and used to predict the RMS currents in the passive components with some non-intuitive results especially concerning the bus capacitors. It is shown in the paper, that the optimum number of phases is dependent on the converter parameters such as the phase inductance and operating requirements. Practical results are presented confirming the synchronous rectifier loss model.