DocumentCode :
1872097
Title :
Structural constraints for circular self-test paths
Author :
Carletta, Joan ; Papachristou, Christos
Author_Institution :
Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
fYear :
1994
fDate :
25-28 Apr 1994
Firstpage :
87
Lastpage :
92
Abstract :
Constraints on the structure of circular self-test paths in register transfer level (RTL) circuits with circular built-in self test (BIST) features are discussed. These constraints arise from the desire to avoid bit-level correlation, which can have a devastating effect on test quality. Two causes of bit-level correlation are examined, with examples demonstrating the resulting degradation in test quality. The first cause, register adjacency, is a byproduct of the ordering of the registers within the circular self test path. The second cause, a correlation inherent in circular BIST, stems from the shifting nature of the circular self-test path
Keywords :
built-in self test; integrated circuit testing; integrated logic circuits; logic testing; BIST; RTL circuits; bit-level correlation; built-in self test; circular self-test paths; register adjacency; register transfer level; structural constraints; test quality; Automatic testing; Built-in self-test; Circuit testing; Clocks; Costs; Degradation; Flip-flops; Registers; Semiconductor device testing; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location :
Cherry Hill, NJ
Print_ISBN :
0-8186-5440-6
Type :
conf
DOI :
10.1109/VTEST.1994.292329
Filename :
292329
Link To Document :
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