Multiple weighted cellular automata

Author

Neebel, Danial J. ; Kime, Charles R.

Author_Institution

Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA

fYear

1994

fDate

25-28 Apr 1994

Firstpage

81

Lastpage

86

Abstract

Presents a complete design method for inhomogeneous cellular automata capable of generating BIST patterns with multiple weight sets at a test per clock rate. The method achieves 100% stuck-at fault coverage of detectable faults for almost all combinational benchmark circuits having random pattern resistant faults. The authors also present data showing the overall speed up relative to test per scan methods

Keywords

boundary scan testing; built-in self test; cellular automata; combinatorial circuits; combinatorial switching; fault location; logic CAD; logic testing; BIST patterns; combinational benchmark circuits; detectable faults; inhomogeneous cellular automata; multiple weight sets; multiple weighted cellular automata; random pattern resistant faults; stuck-at fault coverage; test per scan methods; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Clocks; Design methodology; Electrical fault detection; Fault detection; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1994. Proceedings., 12th IEEE

Conference_Location

Cherry Hill, NJ

Print_ISBN

0-8186-5440-6

Type

conf

DOI

10.1109/VTEST.1994.292330

Filename

292330