DocumentCode
1872163
Title
A design for testability technique for test pattern generation with LFSRs
Author
Kagaris, Dimitrios ; Tragoudas, Spyros
Author_Institution
Comput. Sci. Program, Dartmouth Coll., Hanover, NH, USA
fYear
1994
fDate
25-28 Apr 1994
Firstpage
68
Lastpage
73
Abstract
Test sets for built-in self-test (BIST) test pattern generation (TPG) are normally pseudorandom or truncated pseudoexhaustive. In this work, the authors propose a pseudorandom TPG scheme which is based on the idea of ordering appropriately the cells of a linear feedback shift register (LFSR) in order to control the percentage of linear dependencies in the generated patterns. The LFSR cell ordering is done prior to the circuit´s layout phase, in accordance with the design for testability principles. The proposed pseudorandom scheme compares favorably with the use of truncated pseudoexhaustive test sets with or without cell reordering
Keywords
automatic testing; built-in self test; design for testability; integrated circuit testing; logic testing; sequential circuits; shift registers; LFSRs; built-in self-test; cell ordering; design for testability technique; pseudorandom scheme; test pattern generation; Automatic testing; Built-in self-test; Circuit testing; Computer science; Design for testability; Feedback; Hardware; Polynomials; Strontium; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location
Cherry Hill, NJ
Print_ISBN
0-8186-5440-6
Type
conf
DOI
10.1109/VTEST.1994.292332
Filename
292332
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