• DocumentCode
    187218
  • Title

    GF(24) multiplier in hardware using discrete neural network

  • Author

    Reis, Vanderson Lima ; Costa, Wendell E. M. ; Freire, Raimundo Carlos S. ; De Assis, Francisco M. ; Santana, Eder

  • Author_Institution
    CMDI - IFAM, Manaus, Brazil
  • fYear
    2014
  • fDate
    12-15 May 2014
  • Firstpage
    1144
  • Lastpage
    1147
  • Abstract
    This article describes a new structure of finite fields multiplier based on Mastrovito multiplier. This architecture has linear threshold gates as the processing units, which is the basic element of a discrete neural network. One of the great advantages of using neural networks implemented with discrete linear threshold gates is that it reduces the complexity of certain circuits before implemented with traditional logic (AND, OR, and NOT), thus making more complex circuits can be designed in a more simplified form by reducing the number of necessary ports. The entire circuit was designed and simulated using CADENCE tools with technology IBM018.
  • Keywords
    circuit complexity; logic circuits; logic design; logic gates; neural nets; CADENCE tools; GF(2^4) multiplier; IBM018 technology; Mastrovito multiplier; circuit complexity reduction; circuit design; discrete linear threshold gates; discrete neural network; finite field multiplier; hardware; Clocks; Computer architecture; Galois fields; Logic gates; Neural networks; Ports (Computers); Transistors; GF(24) multiplier; Threshold Logic Gates; discrete neural networks;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Instrumentation and Measurement Technology Conference (I2MTC) Proceedings, 2014 IEEE International
  • Conference_Location
    Montevideo
  • Type

    conf

  • DOI
    10.1109/I2MTC.2014.6860922
  • Filename
    6860922