Title :
Circuit Performance Optimization in Advanced PD-SOI CMOS Development
Author :
Chiang, W.T. ; Huang, Y.T. ; Liu, P.W. ; Wu, C.H. ; Su, C.M. ; Huang, Y.S. ; Tsai, C.H. ; Laplanche, Y. ; Pelloie, J.-L. ; Tsai, C.T. ; Ma, G.H.
Author_Institution :
Central R&D Div., United Microelectron. Corp. (UMC), Tainan
Abstract :
Device optimization on partially-depleted silicon-on-insulator (PD-SOI) CMOS is systematically performed in terms of circuit switching speed and power consumption. The effects of several key factors, such as threshold voltage (Vth), pre-amorphization implantation (PAI), and silicon film thickness (Tsi), are fully investigated and optimized to achieve optimal ring-oscillator performance. We found that well-designed PAI improves circuit delay vs. leakage characteristics, while decreasing Tsi also reduces the propagation delay. We then present the optimized AC performance for a variety of circuits, as well as the DC performance, the SRAM characteristics, and the reliability assessment.
Keywords :
CMOS integrated circuits; circuit optimisation; integrated circuit reliability; leakage currents; silicon-on-insulator; AC performance; DC performance; PD-SOI CMOS development; SRAM characteristics; SiO2-Si; circuit delay; circuit performance optimization; circuit switching speed; leakage characteristics; partially-depleted silicon-on-insulator CMOS; power consumption; pre-amorphization implantation; reliability assessment; ring-oscillator performance; silicon film thickness; threshold voltage; CMOS technology; Circuit optimization; Energy consumption; Frequency; Inverters; Ion implantation; Propagation delay; Semiconductor films; Silicon; Threshold voltage;
Conference_Titel :
SOI Conference, 2007 IEEE International
Conference_Location :
Indian Wells, CA
Print_ISBN :
978-1-4244-0879-5
Electronic_ISBN :
1078-621X
DOI :
10.1109/SOI.2007.4357858
