Title :
Synthesizing designs with low-cardinality minimum feedback vertex set for partial scan application
Author :
Dey, Sujit ; Potkonjak, Miodrag ; Roy, Rabindra
Author_Institution :
NEC Res. Inst., Princeton, NJ, USA
Abstract :
An efficient partial scan approach for cost-effective sequential ATPG is to select flip-flops (FFs) in the minimum feedback vertex set (MFVS) of the FF dependency graph, so that loops are broken. Through a comprehensive analysis of the sources of loops in the data path, this paper proposes a new high-level synthesis methodology to synthesize data paths which have low-cardinality MFVS, thereby reducing the cost of partial scan significantly. A test efficiency of 100% could be achieved for all designs synthesized by the proposed approach, requiring a significantly less number of FFs to be scanned compared to the original implementations
Keywords :
automatic testing; design for testability; integrated circuit testing; integrated logic circuits; logic CAD; logic testing; scheduling; sequential circuits; automatic test pattern generator; data path synthesis; dependency graph; flip-flop selection; high-level synthesis methodology; low-cardinality minimum feedback vertex set; partial scan application; sequential ATPG; Automatic test pattern generation; Circuit synthesis; Circuit testing; Costs; Feedback loop; Flip-flops; High level synthesis; Sequential analysis; Sequential circuits; Signal synthesis;
Conference_Titel :
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location :
Cherry Hill, NJ
Print_ISBN :
0-8186-5440-6
DOI :
10.1109/VTEST.1994.292342
