DocumentCode :
1872503
Title :
3D stacked channels: how series resistances can limit 3D devices performance
Author :
Bernard, E. ; Ernst, T. ; Guillaumot, B. ; Vulliet, N. ; Maffini-Alvaro, V. ; Andrieu, F. ; Lecarval, G. ; Rivallin, P. ; Vizioz, C. ; Campidelli, Y. ; Kermarrec, O. ; Hartmann, J.M. ; Borel, S. ; Delaye, V. ; Pouydebasque, A. ; Souifi, A. ; Coronel, P. ;
Author_Institution :
CEA/LETI, Grenoble
fYear :
2007
fDate :
1-4 Oct. 2007
Firstpage :
93
Lastpage :
94
Abstract :
We have integrated 3D low power multi-channel field effect transistors (MCFETs) with TiN/HfO2 gate stacks. We present, for the first time, a general analytical model explaining quantitatively the experimental current gain of this architecture compared to an optimized planar FD-SOI reference with the same gate stack. The gain is highly dependant on gate and drain voltages. The impact of the series resistances is also amplified in 3D devices. The number of channels and the S/D shape will have to be carefully chosen and optimized in order to minimize those resistances.
Keywords :
field effect transistors; hafnium compounds; low-power electronics; semiconductor device models; silicon-on-insulator; titanium compounds; 3D devices performance; 3D stacked channels; TiN-HfO2; analytical model; current gain; multi-channel field effect transistors; series resistances; silicon-on-insulator; Capacitance-voltage characteristics; Conference proceedings; Delay; FETs; Hafnium oxide; MOSFETs; Numerical simulation; Shape; Tin; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOI Conference, 2007 IEEE International
Conference_Location :
Indian Wells, CA
ISSN :
1078-621X
Print_ISBN :
978-1-4244-0879-5
Electronic_ISBN :
1078-621X
Type :
conf
DOI :
10.1109/SOI.2007.4357868
Filename :
4357868
Link To Document :
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