Analysis of Sensing margin in Silicon-On-ONO (SOONO) Device for the Capacitor-less RAM Applications

Author

Yun, Eun Jung ; Song, Ho Ju ; Hong, Sung In ; Kim, Sung Hwan ; Choi, Yong Lack ; Bae, Hyun Jun ; Kim, Na Young ; Oh, Chang Woo ; Kim, Dong-Won ; Park, Donggun

Author_Institution

R&D Center, Seoul

fYear

2007

fDate

1-4 Oct. 2007

Firstpage

103

Lastpage

104

Abstract

In this study, we compared sensing margin according to the back gate bias and body doping concentration. We achieved large sensing margin of 62 uA/um at L_G = 87 run and demonstrated sensing margin of 45 uA/um with L_G = 47 nm that is the smallest device ever reported for the floating body RAM. For the scaling down to the sub 50 nm gate length, we should reduce the body thickness for the SCE with optimum body doping condition . Possibility of scaling down with the capacitor-less RAM is shown to the sub 50 nm from this result.

Keywords

integrated memory circuits; random-access storage; silicon-on-insulator; SOONO device; back gate bias; body doping concentration; capacitor-less RAM applications; floating body RAM; sensing margin; silicon-on-ONO device; Capacitors; Conference proceedings; Costs; Doping; Insulation; Random access memory; Read-write memory; Research and development; Silicon on insulator technology; Thickness control;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2007 IEEE International

Conference_Location

Indian Wells, CA

ISSN

1078-621X

Print_ISBN

978-1-4244-0879-5

Electronic_ISBN

1078-621X

Type

conf

DOI

10.1109/SOI.2007.4357873

Filename

4357873