Speeding-up adaptive heuristic critic learning with FPGA-based unsupervised clustering

Author

Pérez-Uribe, Andrés ; Sanchez, Eduardo

Author_Institution

Logic Syst. Lab., Swiss Federal Inst. of Technol., Lausanne, Switzerland

fYear

1997

fDate

13-16 Apr 1997

Firstpage

685

Lastpage

689

Abstract

Neurocontrol is a crucial area of fundamental research within the neural network field. Adaptive heuristic critic learning is a key algorithm for real-time adaptation in neurocontrollers. In this paper, we show how an unsupervised neural network model with an adaptable structure can be used to speed-up adaptive heuristic critic learning, present its FPGA design, and show how it adapts the neurocontroller to the state space of the system being controlled

Keywords

adaptive control; field programmable gate arrays; heuristic programming; learning systems; neural chips; neurocontrollers; pattern recognition; state-space methods; unsupervised learning; FPGA-based unsupervised clustering; adaptable structure; adaptive heuristic critic learning; neurocontrol; neurocontroller adaptation; real-time adaptation; speedup; state space; unsupervised neural network model; Algorithm design and analysis; Artificial neural networks; Clustering algorithms; Field programmable gate arrays; Hardware; Heuristic algorithms; Learning; Logic; Neural networks; Neurocontrollers;

fLanguage

English

Publisher

ieee

Conference_Titel

Evolutionary Computation, 1997., IEEE International Conference on

Conference_Location

Indianapolis, IN

Print_ISBN

0-7803-3949-5

Type

conf

DOI

10.1109/ICEC.1997.592405

Filename

592405