Rapid prototyping of a DMSK transceiver

We describe the algorithm architecture development and implementation of a DMSK receiver prototype on a field programmable gate array (FPGA). The algorithm provides fast acquisition as well as a simple implementation and is suited for use in broadcast networks due to the exploitation of the capture phenomenon. During the design process we utilized a novel methodology involving multirate dynamic data flow system level simulation, exploitation of a generic VHDL based implementation library, automatic VHDL generation based on the data flow description and logic synthesis. The advantages and current limitations of this approach as well as the algorithm and implementation trade-offs are discussed