Author :
Ferain, I. ; Son, N.J. ; Witters, L. ; Collaert, N. ; Onsia, Bart ; Kaczer, Ben ; Kauerauf, T. ; Adelmann, C. ; Favia, Paola ; Richard, O. ; Bender, H. ; Van Elshocht, S. ; Lehnen, P. ; San, K.T. ; De Meyer, K. ; Biesemans, S. ; Jurczak, M.
Abstract :
In this work, we investigate the possibility of achieving low VT nMOS FinFETs with single metal gate by using a dysprosium oxide (Dy2O3) cap layer inserted between gate dielectric and metal. We determine an optimum ratio between Dy2O3 and SiO2 gate dielectric thicknesses for low nMOS VT with good process margin and no loss in performance and reliability.
Keywords :
MOSFET; dielectric materials; dysprosium compounds; semiconductor device reliability; silicon compounds; Dy2O3-SiO2 - Interface; device reliability; dielectric cap approach; gate dielectric thicknes; metal gate technology; multiple-VT in NMOS FinFET; process margin; Channel bank filters; Dielectric losses; Dielectric substrates; Electrodes; FinFETs; Gate leakage; MOS capacitors; MOS devices; Performance loss; Tin;
