Title :
Optimizing the Improved Barrett Modular Multipliers for Public-Key Cryptography
Author_Institution :
Dept. of Electron. Eng., Macquarie Univ., Sydney, NSW, Australia
Abstract :
This work is a significant stage of the project, "Digital Arithmetic Public-Key Cryptography". It constructs a modular multiplier for use in the channel of a Residue Number System (RNS). The modular multiplier is implemented on FPGA and optimized by evaluating different versions of the Improved Barrett Algorithm. The resulting optimized multiplier is 12 bits wide and uses separated multiplication and reduction.
Keywords :
digital arithmetic; field programmable gate arrays; public key cryptography; FPGA; digital arithmetic public key cryptography; improved Barrett modular multipliers; public key cryptography; residue number system; Delay; Dynamic range; Field programmable gate arrays; Hardware; Public key cryptography; Signal processing algorithms;
Conference_Titel :
Computational Intelligence and Software Engineering (CiSE), 2010 International Conference on
Conference_Location :
Wuhan
Print_ISBN :
978-1-4244-5391-7
Electronic_ISBN :
978-1-4244-5392-4
DOI :
10.1109/CISE.2010.5676912
