Title :
Timing-Aware Diagnosis for Small Delay Defects
Author :
Aikyo, Takashi ; Takahashi, Hiroki ; Higami, Yoshinobu ; Ootsu, J. ; Ono, Keishi ; Takamatsu, Yusuke
Author_Institution :
Semicond. Technol. Acad. Res. Center, Yokohama
Abstract :
As semiconductor technologies progress, testing of small delay defects are becoming more important for SoCs. However, fault diagnosis of small delay defects has not been developed. We propose a novel timing-aware method for diagnosing small delay defects with a small computation cost using gate delay fault simulation with the minimum detectable delay, as introduced in the statistical delay quality model. The experimental results show that the proposed method is capable of identifying fault locations for small delay defects with a small computation cost.
Keywords :
delays; fault simulation; integrated circuit testing; semiconductor technology; system-on-chip; timing; SoC; fault diagnosis; fault location; gate delay fault simulation; semiconductor technology; small delay defects; statistical delay quality model; timing-aware diagnosis; timing-aware method; Calculus; Circuit faults; Circuit testing; Computational efficiency; Delay effects; Fault detection; Fault diagnosis; Probability; Propagation delay; Timing;
Conference_Titel :
Defect and Fault-Tolerance in VLSI Systems, 2007. DFT '07. 22nd IEEE International Symposium on
Conference_Location :
Rome
Print_ISBN :
978-0-7695-2885-4
DOI :
10.1109/DFT.2007.30