A low power bulk-driven MDAC synapse

Author

Laajimi, Radwene ; Hamdi, Belgacem ; Ayari, Nadia

Author_Institution

Electron. & Microelectron. Lab., Monastir, Tunisia

fYear

2011

fDate

7-8 Sept. 2011

Firstpage

1

Lastpage

5

Abstract

Efficient weight storage and multiplication are important design challenges which must be addressed in analog neural network implementations. Many schemes have been previously reported for implementation of synapses. In this paper we describe a buck driven Multiplier digital-to-analog converter (MDAC) circuit. We present a novel synapse circuit for analog neural networks. This circuit is a 6-bit Multiplier Digital to Analogue Converter (MDAC) synapse based on bulk-driven technology. The circuit has a small layout area (1200 μm2 using 0.18 μm TSMC CMOS technology). The measured results are within ±0.5 LSB for DNL and ±0.4 LSB for INL, with 0.1 mW power dissipation at 0.75 V power supply and the silicon area is reduced by a factor of 35% with respect to conventional MDAC implementation.

Keywords

CMOS integrated circuits; analogue integrated circuits; digital-analogue conversion; integrated circuit design; multiplying circuits; neural nets; 6-bit MDAC synapse; TSMC CMOS technology; VLSI circuits; analog neural networks; deep-n-well process; differential nonlinearity; integral nonlinearity error; low power bulk-driven MDAC synapse; multiplier digital-analog converter circuit; multiplying DAC design; power dissipation; size 0.18 mum; storage capacity 6 bit; voltage 0.75 V; Biological neural networks; CMOS integrated circuits; CMOS technology; Layout; Mirrors; Neurons; Very large scale integration; Bulk-driven technology; Deep-N-Well; Low power; Multiplying DAC;

fLanguage

English

Publisher

ieee

Conference_Titel

Applied Electronics (AE), 2011 International Conference on

Conference_Location

Pilsen

ISSN

1803-7232

Print_ISBN

978-1-4577-0315-7

Electronic_ISBN

1803-7232

Type

conf

Filename

6049045