FPGA-based multi-phase digital pulse width modulator with dual-edge modulation

This paper proposes a new FPGA-based architecture for a multi-phase digital pulse width modulator (MP-DPWM). A novel fine-leading/coarse-trailing edge modulation is applied to allow the sharing of a single fine resolution block for all phases. Specifically, the architecture takes advantage of Digital Clock Manager (DCM) blocks available in modern FPGAs to produce four clock phases from a single clock input to increase the resolution by two bit. An optimized counter/shift-register block is detailed which reduces the size and increases the maximum clock frequency of the architecture for certain numbers of phases. The design was successfully implemented on a low-cost Xilinx Spartan-3 FPGA 9-bit resolution with a switching frequency of 1 MHz and 2-16 phases.