Title :
Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections
Author :
Maistri, P. ; Vanhauwaert, P. ; Leveugle, R.
Author_Institution :
TIM A Lab., Grenoble
Abstract :
Some protection techniques had been previously proposed for encryption blocks and applied to an AES encryption IP described at RT Level. One of these techniques had been validated by purely functional fault injections (i.e. algorithmic-level fault injections) against single- and multiple- bit errors. RT-Level fault injections have been performed recently on a few AES IPs and this paper summarizes the main results obtained, highlighting the new results and comparing the outcomes of the two fault injection levels.
Keywords :
cryptography; encryption standard; multilevel fault injection; register-level protection techniques; Algorithm design and analysis; Computational modeling; Cryptography; Error correction; Fault tolerant systems; Hardware; Protection; Single event upset; Testing; Very large scale integration;
Conference_Titel :
Defect and Fault-Tolerance in VLSI Systems, 2007. DFT '07. 22nd IEEE International Symposium on
Conference_Location :
Rome
Print_ISBN :
978-0-7695-2885-4
DOI :
10.1109/DFT.2007.41
