A Hybrid Evolution Algorithm for VLSI Floorplanning

Author

Chen, Jiarui ; Chen, Jianli

Author_Institution

Center for Discrete Math. & Theor. Comput. Sci., Fuzhou Univ., Fuzhou, China

fYear

2010

fDate

10-12 Dec. 2010

Firstpage

1

Lastpage

4

Abstract

The floorplanning is a critical phase in very large-scale integrated-circuit(VLSI) physical design. It determines the topology of layout, and it aims to arrange a set of rectangular modules on a chip so as to optimize the chip area, wirelength, etc. This problem is known to be NP-hard, and has received much attention in recent years. B*-tree representation is adopted in this paper. Based on the concept of evolutionary algorithm and simulated annealing, a hybrid evolutionary algorithm(ESA) is proposed. It is effective to explore solution space and locate the optimal solution. The effectiveness of our method is demonstrated on several cases of MCNC benchmarks.

Keywords

VLSI; evolutionary computation; integrated circuit layout; network topology; simulated annealing; trees (mathematics); B*-tree representation; VLSI floorplanning; evolutionary algorithm; hybrid evolution algorithm; simulated annealing; topology; very large-scale integrated-circuit; Algorithm design and analysis; Benchmark testing; Computational modeling; Integrated circuit modeling; Simulated annealing; Space exploration; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computational Intelligence and Software Engineering (CiSE), 2010 International Conference on

Conference_Location

Wuhan

Print_ISBN

978-1-4244-5391-7

Electronic_ISBN

978-1-4244-5392-4

Type

conf

DOI

10.1109/CISE.2010.5676951

Filename

5676951