Modeling of Delta-I noise in digital electronics packaging

Delta-I noise, which refers to the voltage fluctuations between power and ground conductors caused by sudden current surges, has been well recognized as a limiting factor for the reliable operation of high-speed integrated circuits. A novel technique for modeling Delta-I noise associated with power and ground planes is presented in this paper. This new approach considers not only the wave propagation and resonance in power and ground planes, also the geometry of the interconnections such as the via radius, which results in accurate prediction of the Delta-I noise waveforms. An electromagnetic field solver is employed to model the power/ground planes connected with vias, and is linked to SPICE type circuit solvers to analyze the components off the planes. This simulation technique is found to be very fast in computation speed and also highly accurate. Simulation results are provided together with a comparison of Delta-I analysis performed by the method of this paper and IBM´s ASTAP