Title :
Laminated memory: a new 3-dimensional packaging technology for MCMs
Author :
Tuckerman, D.B. ; Bauer, L.-O. ; Brathwaite, N.E. ; Demmin, J. ; Flatow, K. ; Hsu, R. ; Kim, P. ; Lin, C.-M. ; Lin, K. ; Nguyen, S. ; Thipphavong, V.
Author_Institution :
nChip Inc., San Hose, CA, USA
Abstract :
A new, low-cost, manufacturable process for stacking memory chips up to four-high on a multichip module (MCM) substrate is described. The process is particularly useful when utilized with a high-performance thin-film interconnection substrate (“MCM-D”), as the technique typically enables large (2-4x) reductions in substrate cost for memory-intensive designs, with only a small increment in assembly cost, thereby achieving lower total MCM cost, and greater utilization of the high wiring density and good thermal conductivity of the MCM substrate. The technology was developed and demonstrated using commercially available MCM assembly equipment (dicing, adhesive die attach, and wire bonding equipment). Fully functional memory modules incorporating 2-high stacks have been fabricated, and have passed basic thermal shock tests
Keywords :
VLSI; economics; integrated circuit manufacture; integrated memory circuits; multichip modules; 3D packaging technology; MCM cost; MCM-D; MCMs; adhesive die attach; assembly cost; dicing; functional memory modules; high wiring density; high-performance thin-film interconnection substrate; laminated memory; memory chip stacking; memory-intensive design; multichip module substrate; substrate cost; substrate thermal conductivity; thermal shock tests; wire bonding equipment; Assembly; Costs; Manufacturing processes; Multichip modules; Packaging; Stacking; Substrates; Thermal conductivity; Transistors; Wiring;
Conference_Titel :
Multi-Chip Module Conference, 1994. MCMC-94, Proceedings., 1994 IEEE
Conference_Location :
Santa Cruz, CA
Print_ISBN :
0-8186-5560-7
DOI :
10.1109/MCMC.1994.292526
