A high-efficiency HEVC entropy decoding hardware architecture

High Efficiency Video Coding (HEVC) is becoming more and more important in current consumer application platforms. Compared with H264 standard, it can reach up to 8192×4320 resolutions at 120fps. To accelerate HEVC decoding processing, this paper presents an efficient hardware entropy decoding architecture, Entropy decoding includes Colomb and CABAC decoding. Hierarchy ring buffer is designed to storage input bit-stream; Stack based Quad-Tree decoding structure is proposed for bit-stream parsing. Since CABAC decoder is a well-known bottleneck of the decoding performance, a 5-stage pipelined CABAC decoding engine is designed to accelerate the serial decoding progress. The proposed entropy decoding hardware architecture is verified on Altera Stratix TV FPGA running at a 200MHz clock frequency, using 8404 slices, memory size is 204KB.