DocumentCode
1875952
Title
Implementation of Sigma-Delta Analog to Digital Converter in FPGA
Author
Mihálov, Jozef ; Stopjaková, Viera
Author_Institution
Dept. of Microelectron., Slovak Univ. of Technol., Bratislava, Slovakia
fYear
2011
fDate
7-8 Sept. 2011
Firstpage
1
Lastpage
4
Abstract
This paper presents implementation of a second-order Sigma-Delta Analog to Digital Converter (ADC) for audio band in field-programmable gate array (FPGA) Xilinx Virtex5. This family of FPGA contains a differential input buffers, which are used to create a continuous-time integrators as a loop filter stages. The implementation is done using hardware description language (VHDL).
Keywords
field programmable gate arrays; hardware description languages; sigma-delta modulation; FPGA Xilinx Virtex5; continuous-time integrators; field-programmable gate array; hardware description language; loop filter stages; second-order sigma-delta analog-digital converter; Capacitors; Clocks; Field programmable gate arrays; Noise; Resistors; Sigma delta modulation; Signal resolution;
fLanguage
English
Publisher
ieee
Conference_Titel
Applied Electronics (AE), 2011 International Conference on
Conference_Location
Pilsen
ISSN
1803-7232
Print_ISBN
978-1-4577-0315-7
Electronic_ISBN
1803-7232
Type
conf
Filename
6049121
Link To Document