DocumentCode :
1876076
Title :
Reducing common-mode voltage in three-phase sine-triangle PWM with interleaved carriers
Author :
Kimball, Jonathan W. ; Zawodniok, Maciej
Author_Institution :
Dept. of Electr. & Comput. Eng., Missouri Univ. of Sci. & Technol., Rolla, MO, USA
fYear :
2010
fDate :
21-25 Feb. 2010
Firstpage :
1508
Lastpage :
1513
Abstract :
Interleaving PWM waveforms is a proven method to reduce ripple in dc-dc converters. The present work explores interleaving for three-phase motor drives. Fourier analysis shows that interleaving the carriers in conventional uniform PWM significantly reduces the common-mode voltage. New DSP hardware supports interleaving directly with changes to just two registers at setup time, so no additional computation time is needed during operation. The common-mode voltage reduction ranges from 36% at full modulation to 67% when idling with zero modulation. Third harmonic injection slightly reduces the advantage (to 26% at full modulation). However, the maximum RMS common-mode voltage is still less than 20% of the bus voltage under all conditions. Low-voltage experimental results support the findings.
Keywords :
DC-DC power convertors; Fourier analysis; PWM power convertors; digital signal processing chips; DSP hardware; Fourier analysis; common-mode voltage reduction; dc-dc converter ripple reduction; harmonic injection; interleaved PWM carriers; three-phase motor drives; three-phase sine-triangle PWM; DC-DC power converters; Frequency; Hardware; Harmonic analysis; Interleaved codes; Motor drives; Pulse width modulation; Signal analysis; Support vector machines; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Applied Power Electronics Conference and Exposition (APEC), 2010 Twenty-Fifth Annual IEEE
Conference_Location :
Palm Springs, CA
ISSN :
1048-2334
Print_ISBN :
978-1-4244-4782-4
Electronic_ISBN :
1048-2334
Type :
conf
DOI :
10.1109/APEC.2010.5433431
Filename :
5433431
Link To Document :
بازگشت