DocumentCode
187630
Title
A voltage base electrothermal model for the interconnection and E-Fuse under the DC and pulse stresses
Author
Jian-Hsing Lee ; Prabhu, M. ; Iyer, Natarajan M. ; Cheng-Hsu Wu ; Chen-Hsin Lien
Author_Institution
Reliability Eng. Dept., GLOBALFOUNDRIES Inc., Malta, NY, USA
fYear
2014
fDate
1-5 June 2014
Abstract
A DC and pulse stress electro-thermal model that can well describe the dynamic thermal behaviors of most interconnections fabricated in CMOS technology is derived and demonstrated. This model provides for the first time a simple methodology to evaluate the time dependent temperature and resistance of the interconnection under an applied voltage stress, especially critical to E-Fuse development.
Keywords
CMOS integrated circuits; integrated circuit interconnections; CMOS technology; DC stress; E-Fuse; applied voltage stress; dynamic thermal behaviors; interconnection; pulse stress; time dependent temperature; voltage base electrothermal model; Electrical resistance measurement; Resistors; Stress; Temperature measurement; Thermal resistance; Thermal stresses; E-Fuse; Electrothermal; formatting;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium, 2014 IEEE International
Conference_Location
Waikoloa, HI
Type
conf
DOI
10.1109/IRPS.2014.6861135
Filename
6861135
Link To Document