Voltage pulse stress effect on gate stack TDDB distributions at nanometric scale: Consequence on aging by ESD

Author

Foissac, R. ; Blonkowski, S. ; Gros-Jean, M. ; Kogelschatz, M.

Author_Institution

STMicroelectron., Crolles, France

fYear

2014

fDate

1-5 June 2014

Abstract

The effects of a voltage pulse stress on time to breakdown and breakdown voltage distributions of a 1.4nm thick SiON layer are investigated at nanometric scale using an atomic force microscope in conduction mode under ultra-high vacuum. Thanks to the reduced tip/sample contact area, a large window of voltage pulse amplitude and length is allowed. It is found that the pre-stress pulse does impact the slope of the cumulative failure distribution but has no effect on the voltage acceleration factor. Using this assumption an extrapolation formula is given to predict the decrease of the time to breakdown as a function of the pre-stress pulse parameters.

Keywords

CMOS integrated circuits; ageing; atomic force microscopy; electric breakdown; electrostatic discharge; failure analysis; integrated circuit reliability; nanoelectronics; silicon compounds; stress analysis; voltage distribution; CMOS devices; ESD; SiON; aging; atomic force microscope; breakdown voltage distributions; conduction mode; cumulative failure distribution; extrapolation formula; gate stack TDDB distributions; nanometric scale; pre-stress pulse parameter function; reduced tip-sample contact area; size 1.4 nm; time to breakdown distribution; ultra-high vacuum; voltage acceleration factor; voltage pulse amplitude window; voltage pulse stress effect; Acceleration; Degradation; Electrostatic discharges; Logic gates; Reliability; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium, 2014 IEEE International

Conference_Location

Waikoloa, HI

Type

conf

DOI

10.1109/IRPS.2014.6861148

Filename

6861148