A new approach for obtaining all logic gates using Chua´s circuit with fixed input/output levels

Author

Rizk, Mohamed R M ; Nasser, Abdel-Menem A. ; El-badawy, El-sayed A. ; Abou-Bakr, Ehab

Author_Institution

EE Dept., Alexandria Univ., Alexandria, Egypt

fYear

2012

fDate

6-9 March 2012

Firstpage

12

Lastpage

17

Abstract

This paper presents a universal logic gate to perform all logic functions, namely, AND, OR, NAND, NOR, and XOR operations without changing the circuit topology. The basic advantage behind our scheme is that there is no need for level conversion between logic levels at the gate terminals (direct hardwiring). The circuit used for verifying the above functions is the Chua´s circuit (continuous time domain). VHDL-AMS verification is included to show the validity of the proposed gate.

Keywords

Chua´s circuit; hardware description languages; logic design; logic gates; network topology; Chua´s circuit; NAND operation; NOR operation; VHDL-AMS verification; XOR operation; circuit topology; fixed input-output level; logic function; universal logic gate; Chaotic communication; Equations; Integrated circuit modeling; Logic functions; Logic gates; Time domain analysis; Chua´s circuit; Universal logic gate; VHDL-AMS;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Communications and Computers (JEC-ECC), 2012 Japan-Egypt Conference on

Conference_Location

Alexandria

Print_ISBN

978-1-4673-0485-6

Type

conf

DOI

10.1109/JEC-ECC.2012.6186948

Filename

6186948