DocumentCode :
1876602
Title :
Intelligent Task Mapping Using Machine Learning
Author :
Tetzlaff, Dirk ; Glesner, Sabine
Author_Institution :
Group Software Eng. for Embedded Syst., Berlin Inst. of Technol., Berlin, Germany
fYear :
2010
fDate :
10-12 Dec. 2010
Firstpage :
1
Lastpage :
4
Abstract :
Task scheduling and task allocation, which are vital parts of mapping parallel programs to concurrent architectures, must take into account the interprocessor communication, whose overheads have emerged as the major performance limitation in parallel applications. Furthermore, its power consumption is an important research focus which must be addressed. Finding an optimal solution requires information about the runtime behavior, which is not known at compile time. Moreover, the computational complexity leads to heuristic approaches based on conservative assumptions that are unable to exploit all of the program´s optimization potential. In this paper, we propose a novel approach to automatically generate architecture- and application-specific heuristics for power- and communication-aware task mapping using machine learning techniques to predict how programs behave at runtime. The key advantage of machine learning techniques is their ability to find relevant information in a high-dimensional space. This yields more precise heuristics than those based on pure static assumptions, as our experimental results show. Because learning is done in an off-line training phase once per architecture, the compile time itself is not extended as in other heuristic approaches like genetic or evolutionary algorithms.
Keywords :
computational complexity; concurrency control; genetic algorithms; learning (artificial intelligence); parallel programming; power aware computing; program compilers; program diagnostics; scheduling; software architecture; task analysis; communication-aware task mapping; compile time; computational complexity; concurrent architectures; evolutionary algorithms; genetic algorithms; intelligent task mapping; interprocessor communication; machine learning techniques; off-line training phase; parallel program mapping; power consumption; power-aware task mapping; program optimization potential; static assumptions; task allocation; task scheduling; Computer architecture; Heuristic algorithms; Machine learning; Processor scheduling; Resource management; Runtime; Training;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computational Intelligence and Software Engineering (CiSE), 2010 International Conference on
Conference_Location :
Wuhan
Print_ISBN :
978-1-4244-5391-7
Electronic_ISBN :
978-1-4244-5392-4
Type :
conf
DOI :
10.1109/CISE.2010.5677019
Filename :
5677019
Link To Document :
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